1. Field of the Invention
The present invention relates to a display panel substrate, a display panel having the substrate, and a method of correcting the display panel. More specifically, the present invention relates to a display panel substrate having a layer structure of a conductor film, a semiconductor film, and an insulating film of given patterns, e.g., a liquid crystal display panel substrate, a display panel having the substrate, and a method for correcting the display panel.
2. Description of the Related Art
A generally used active matrix type liquid crystal display panel is configured such that a TFT array substrate and a common substrate are placed opposed to each other having a minute gap therebetween, and liquid crystals are filled between the substrates.
FIG. 18 is a schematic plan view of an example of a conventional configuration of a TFT array substrate. On one side of a TFT array substrate 9, an active region 91 is provided. The active region 91 has a matrix arrangement of a plurality of pixel electrodes (not shown) and switching elements (not shown) arranged to drive the respective pixel electrodes. The active region 91 is provided with a plurality of data signal lines 911 arranged to drive the switching elements and a plurality of gate signal lines 912.
In a region outside of the active region 91, drawing lines 921 arranged to transmit source signals to the respective data signal lines 911 are provided. One end of each of the drawing lines 921 is electrically connected to the respective data signal line 911 at the edge of the active region 91, and the other end of the drawing line 921 is connected to a land which is provided at the edge of the TFT array substrate 9.
If electric resistances of the drawing lines are different to one another or capacitances generated between the drawing lines and other conductors in the vicinities thereof (e.g., capacitances generated between the adjacent drawing lines, capacitances generated between the drawing lines and conductor films which overlap with the drawing lines with insulating films sandwiched therebetween; hereinafter referred to as parasitic capacitances) are different to one another, the forms of delay of source signals to be transmitted to the data signal lines could be different among the drawing lines. If the forms of delay of source signals are different among the data signal lines, display irregularity could occur in an image displayed on a display panel. Therefore, it is preferable that the electric resistances and the parasitic capacitances are made uniform among the drawing lines.
The drawing lines are generally configured such that bundles each having a given number of drawing lines converge from the edge of the active region to the edge of the TFT array substrate. To be specific, the drawing lines are divided into bundles each having a given number of drawing lines, and each of the bundles of the drawing lines converges from the edge of the active region to the edge of the TFT array substrate and thus has a taper shape. Therefore, the drawing lines in each bundle are configured such that the length of the drawing line in the center of the bundle is shorter, and the length of the drawing line farther from the center of the bundle is longer. Thus, the lengths of the drawing lines in each bundle are different to one another.
The electric resistances and the parasitic capacitances of the drawing lines could be different according to the lengths of the drawing lines. Therefore, display conditions of pixel groups which receive source signals through the drawing lines of different lengths (and data signal lines connected to the drawing lines) could be different among one another.
Because the lengths of the drawing lines in each bundle gradually differ from the center to either side of the bundle, the electric resistances and the parasitic capacitances also gradually differ from the center to either side of the bundle. Accordingly, the display conditions could gradually differ from the pixel group which receives source signals through the drawing line at the center of the bundle (and the data signal line connected to the drawing line) toward the pixel group which receives source signals through the drawing line on either side of the bundle (and the data signal line connected to the drawing line). Because such a bundle of drawing lines is provided in a plurality, there is a possibility that a plurality of gradual differences in display could occur as a whole in the image displayed on the display panel, and display irregularity in the form of longitudinal streaks could occur on the display panel.
Such display irregularity easily occurs due to the recent increase in the size of the display panel. To be specific, the lengths of the data signal lines are increased by the increase in the size of the display panel, and the electric resistances and the parasitic capacitances of the data signal lines are accordingly increased. Thus, larger loads are put on source drivers, thereby easily causing delay of source signals. Thus, an influence of the differences in the electric resistances and the parasitic capacitances among the drawing lines is easily exerted on the display conditions.
In order to prevent the occurrence of display irregularity, loads on the source drivers are to be reduced. For example, a pair of source drivers are used to transmit source signals from the both ends of each of the data signal lines. However, this configuration increases the number of components and the number of processes as compared to the configuration of inputting source signals from one end of each of the data signal lines. Accordingly, the production cost and the product price could be increased.
Alternatively, the lengths of the drawing lines are made uniform in order to make the electric resistances uniform. In addition, the drawing lines are provided with parasitic capacitances in order to make display uniform (see Japanese Patent Application Unexamined Publication No. 2006-106676). In this configuration, a conductor film is formed on the drawing lines with an insulating film sandwiched therebetween in order to provide parasitic capacitances between the drawing lines and the conductor film.
However, this configuration has a problem as described below. For example, if a conductive foreign particle adheres to the surface of a TFT array substrate in a step of producing a substrate, the foreign particle could pass through the insulating film provided between the drawing line and the conductor film and electrically develop a short between the drawing line and the conductor film. If the drawing line and the conductor film are shorted, given source signals cannot be transmitted to the data signal line connected to the drawing line. As a result, a streak display defect occurs along the data signal line. It is difficult for the configuration of Japanese Patent Application Unexamined Publication No. 2006-106676 to correct such a display defect.